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? 200 2 si lico n st ora ge te chno log y, i nc. s711 72-0 5-00 0 2/ 02 52 3 1 t he sst l ogo a nd sup erf lash a re regi ste red t rade marks of si lico n sto rage te chno logy, i nc. c oncu rrent supe rfl ash, csf, an d comb omemo ry are t rade marks of si lico n sto rage te chno logy, i nc. th ese spe cif icat io ns are sub ject to ch ang e wit ho ut n ot ice. data sheet features: ? flash organization: 1m x16 dual-bank architecture for concurrent read/write operation ? 16 mbit: 12 mbit + 4 mbit sram organization: ? 2 mbit: 256k x8 or 128k x16 ? 4 mbit: 512k x8 or 256k x16 single 2.7 -3 .3 v r ea d and w rit e opera tions superior reliability ? end ur an ce: 10 0,0 00 cycle s ( typica l) ? greater than 100 years data retention low power consumption: ? active current: 25 ma (typical) ? sta n dby cu rr en t: 20 a (typi cal) hardware sector protection (wp#) ? protects 4 outer most sectors (4 kword) in the larger bank by holding wp# low and unprotects by h old in g w p# hig h ha rdwa re re se t pin ( rst#) ? resets the internal state machine to reading data array sec tor-eras e c apa bilit y ? un ifo r m 1 kwor d se cto rs block-erase capability ? uniform 32 kword blocks read access time ? fla sh: 70 an d 9 0 n s ? sram: 70 and 90 ns latched address and data fast erase and word -program: ? sector -era se tim e: 18 ms (typi cal) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? wo rd -prog ra m time : 14 s (typi cal) ? chip rewrite time: 8 seconds (typical) automatic write timing ? internal v pp generation end-of -writ e detection ? tog g le bit ? data# poll ing ? ready/busy# pin cmos i/o compatibility jedec standard command set con forms to common flash memory interface (c fi) packages available ? 56-ball lfbga (8mm x 10mm) product description the sst3 4hf1621/1641 combomemo ry devices inte- grate a 1m x16 cmos fla sh memor y bank with a 256 k x8/ 128k x16 or 512 k x8 / 256k x16 cmos sram me mory bank in a multi-chip package (mcp). th ese d evices a re fabricated usin g sst?s proprietary, high -perfor ma nce cmos superflash technology incorpo rating the sp lit-gate ce ll design and th ick oxid e tunne lin g injector to a tta in b etter reliability and m anufacturab ility compared with alternate appro ach es. the SST34HF1621 /164 1 devices a re ideal for application s such as cellular pho nes, gpss, pdas an d oth er por table electronic d evices in a low p owe r and small form factor system. the SST34HF1621/164 1 fea tures d ual flash memor y b ank architectu re allowing for concurrent ope rations b etween th e two fla sh me mory banks a nd th e sram. th e devices ca n read data from either bank wh ile an era se or pro gram operation is in pro gress in th e o pposite bank. the two flash memory banks a re p artitioned into 4 mbit and 12 mbit with top o r bottom sector protection op tions for stor in g boot co de, pro gram cod e, config uration /para meter da ta an d user da ta. the sup erflash techno lo gy provides fixed erase and pro - gram times, ind epen dent of th e numbe r o f erase/prog ra m cycles that have o ccurre d. there fore, the system software or h ardware doe s not have to b e mo dified or de-rated as is necessary with alte rnative flash techno logies, wh ose erase a nd pro gram times in cre ase with a ccumu lated erase/prog ra m cycle s. the sst34hf16 21/1641 d evices offer a guara nte ed end urance of 1 0,0 00 cycles. data retentio n is rated at gre ate r than 10 0 yea rs. with high pe r- forma nce word -progra m, the fla sh memor y banks pr ovide a typ ica l word-program time of 14 se c. the entire flash memor y ban k can be erased an d programme d wo rd-by- word in typically 8 seco nds for the sst34hf162 1/1 641, when using interfa ce features such as to ggle bit or data# polling to indicate the co mpletio n o f progra m op eratio n. to protect again st in advertent flash write, th e sst34 hf1 621/ 164 1 d evices con tain on -ch ip hardware a nd so ftwa re data protection sch emes. 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 sst3 4hf 16 21/ 164 116 mb csf (x1 6) + 2mb / 4mb sram (x8/ x16 ) mcp co mbome morie s
2 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 the flash a nd sram operate a s two indepe nden t me mory banks with respective bank enable signa ls. the me mory bank selection is do ne by two b ank enable signa ls. th e sram b ank enable sign al, bes1# and bes2 , selects th e sram bank. the flash memo ry ban k enable sig nal, bef#, has to be use d with so ftware da ta pro tection (sdp) com- mand se quence wh en contro lling the erase an d pro gram operations in the flash memory ba nk. the me mory banks are su perimposed in th e same memor y add ress sp ace where they sha re co mmon add ress lines, data lines, we# and oe# which minimize power con su mp tion and area. bus contention is eliminated as the device will not recog- nize both b ank en ables as be in g simultan eously active. desig ned, manufa ctured, and teste d for applications re quir- ing low power and small form facto r, the sst3 4hf1621/ 1641 are offered in both commercial a nd exte nded temp er- atu res a nd a small footprint package to mee t boa rd sp ace co nstraint requ ire ments. device operation the SST34HF1621/1641 uses bes1#, bes2 a nd bef# to co ntrol o peratio n of eith er th e flash o r the sram me mory bank. when bef# is low, the flash bank is activa ted for read, program or erase operation. wh en bes1# is low, and bes2 is h ig h the sram is a ctivated for read an d write operation. bef# a nd bes1# ca nnot be a t low level, and bes2 cann ot be at high level a t the sa me time. if all bank e nable signa ls are a sser ted, bus con tention w ill result and the device may suffer pe rmane nt d amage. all a ddress, data, and con trol lines are sh ared by flash and sram memory banks which minimizes power con su mption an d loading . the device go es into stan dby when bef# an d bes1# b ank enable s a re raised to v ih c (logic high) or when bef# is high and bes2 is low. concurrent read/write operation dual bank a rch itecture of sst34hf162 1/16 41 devices allows th e concurrent rea d/wr ite opera tion whereby th e user can read from one ban k while pro gram or erase in th e oth er b ank. th is operation ca n b e u sed whe n the user need s to re ad system code in o ne ba nk while up datin g data in the o ther bank. see figure 1 fo r dual-ban k me mory orga nization. note: for th e p urp ose s of this t able, write mea ns to blo ck-, sect or, or chip-erase, or word-program as applicable to the appropriate bank. flash read operation th e re ad op er ati on o f th e sst3 4h f16 2 1/1 6 41 i s controlled by bef# and oe#, both have to be low for the system to obtain data from the outputs. bef# is use d fo r d evic e se le ctio n. w he n bef# i s hi gh , th e chip is deselected and only standby power is con- sumed. oe# is the output control and is used to gate da ta fr om th e o u tpu t pi ns. th e d ata bu s is in h ig h impedance state when either bef# or oe# is high. refer to the read cycle timing diagram for further details (figure 6). flash word-program operation th e SST34HF1621 /164 1 are pro gra mmed o n a word-by- word basis. befo re program op eration s, the me mory mu st be erased first. the program op eration co nsists of thre e steps. the first step is the three-byte load seq uence for software data protectio n. the se co nd step is to loa d wo rd addre ss an d word d ata. during th e word-pro gram ope ra- tion, the add resses a re la tched on the fa lling ed ge of eith er bef# or we# , whicheve r occu rs la st. the data is latche d on the rising edge of eithe r bef# or we#, wh ichever occurs first. the th ird step is the inte rnal program o peratio n which is initiated after the risin g edge o f th e four th we# or bef#, whichever occurs first. the program o peratio n, o nce initiated, will be completed typically within 10 s. see fig- ures 7 and 8 fo r we# and bef# co ntro lled pro gram ope ra- tion timing diag ra ms and figure 21 for flowcharts. durin g the pro gram o peratio n, the on ly valid reads are da ta# poll- ing an d to ggle bit. dur in g th e inte rnal pro gram ope ra tion, the host is free to perfor m add itional tasks. an y co mma nds issued durin g the in tern al pro gram op eration are ignore d. c oncurrent r ead /w rite s tate t able flash sram bank 1 bank 2 read write no operation write read no operation write no operation read no operation write read write no operation write no operation write write
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 3 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 flash sector/block-erase operation the se ctor/blo ck-erase op eration allows the system to erase the device on a sector-by-sector o r block-by-blo ck basis. the sst34hf162 1/16 41 offer both secto r-erase and blo ck-erase mode. the sector architecture is ba se d on unifor m sector size of 1 kwo rd. the block-era se mod e is based on u niform block size of 32 kword . the se ctor- erase op eration is in itiate d by executin g a six-byte com- mand seq uence with secto r-erase command (30h) an d se ctor address (sa) in the last bu s cycle. the block-erase operation is initiated by executin g a six-byte comman d se quence with blo ck-erase comman d (50h) and blo ck addre ss (ba) in the la st bus cycle . the sector or blo ck addre ss is latche d on th e fa lling edge of the sixth we# pulse, while the comma nd (30 h or 50 h) is latch ed o n th e rising e dge of the sixth we# pulse. th e in ter nal erase operation begins afte r th e sixth we# pu lse. se e figures 1 2 and 13 fo r timing waveforms. any co mma nds issue d durin g the se ctor- or block-era se ope ra tion are ignored . flash chip-erase operation the sst3 4hf1 621/1641 provid e a chip -erase ope ra tion, which a llows the use r to erase all unpro tected sectors/ blocks to the ?1? state. this is u seful when the d evice mu st be quickly erased. the chip-era se operation is initiated by exe cuting a six- byte command sequen ce with chip-erase command (10h) at a ddress 5555 h in the last byte sequ ence. the erase operation begins with the r ising edge of th e sixth we# or bef#, whichever occurs first. dur in g the erase ope ra tion, the on ly valid read is tog gle bit or data# pollin g. see ta ble 4 fo r the co mmand sequ ence, figu re 11 for timing diagram, and figu re 24 for the flo wchar t. any command s issued d ur- ing the chip-erase operation a re igno red. flash w ri te operati on statu s detecti on the sst34 hf162 1/164 1 pr ovide o ne h ardwa re an d two soft ware m ean s t o de tect th e co mple tio n of a w rite (pro - gram or erase) cycle, in order to optimize the system write cycle time. th e hard ware d ete ctio n uses the read y/busy# (ry/by#) p in. the software de te ction includes two status bits: data# polling (dq 7 ) a nd to ggle bit (dq 6 ) . the end -of-write d etectio n mod e is en abled afte r the rising ed ge of we#, wh ich in itia tes th e in te rna l pro gram or erase ope ration. th e actua l comple tion of the nonvo latile write is asynch ro- nous with the syste m; therefo re, either a ready/busy# (ry/ by# ), data# po llin g (dq 7 ) or toggle bit (dq 6 ) read may be simultaneou s with the comp le tion o f th e write cycle. if this occurs, the syste m may possibly get an erroneo us result, i.e., va lid data may appea r to conflict with either dq 7 or dq 6 . in ord er to preven t spu rious re je ction, if an errone ous result occu rs, the softwa re routin e sho uld inclu de a loop to read th e accessed lo ca tion an add itional two (2) times. if both reads are valid, then the d evice has complete d th e write cycle, othe rwise the rejection is va lid. ready/busy# (ry/by#) th e sst3 4hf1 621/1641 includ es a ready/busy# (ry/ by# ) output signa l. ry/by# is active ly pu lle d low durin g inter nal program/erase operation. the status of ry/by# is valid after the risin g edge of four th we# (o r ce#) p ulse for program o peratio n. for sector-, block- or ba nk-erase, th e ry/by# is valid after the risin g e dge of sixth we# or (ce#) pulse. ry/by# is an ope n drain outp ut that allows several devices to be tied in parallel to v dd via an exte rnal pu ll u p resistor. read y/busy# is in h ig h impe dance whe never oe# or ce# is high or rst# is low. flash data# polling (dq 7 ) when th e SST34HF1621 /164 1 a re in th e interna l pro gram operation, any attempt to read dq 7 will produce the com- plement of th e true d ata. once th e program ope ration is co mpleted , dq 7 will pr oduce tr ue data. note th at eve n tho ugh dq 7 may have valid data immediate ly following th e co mpletion of an inte rnal w rite operation, the remainin g data outputs may still b e invalid: valid d ata on th e entire data bus will a ppear in su bse quent successive rea d cycles after an inte rval of 1 s. dur in g internal erase ope ra- tion, any attemp t to read dq 7 will produce a ?0?. once th e inter nal era se operation is completed, dq 7 will produce a ?1?. the data# polling (dq 7 ) is valid a fte r the risin g edge of four th we# (or bef#) p ulse for program opera tion. for secto r-, block- or chip-erase, the data # po lling (dq 7 ) i s valid after the risin g edge o f sixth w e# (or bef# ) p ulse. after the completion of a pro gram operation, data# pollin g on dq 7 remains active an d th e device may n ot retur n to th e read mode for approximate ly 1 s. se e figure 9 for data # polling (dq 7 ) timing diagram and fig ure 2 2 fo r a flowch art.
4 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 flash toggle bit (dq 6 ) during the inte rnal program or erase ope ration, a ny co n- se cutive attempts to read dq 6 will pr oduce a ltern ating 1s and 0s, i.e., to ggling betwee n 1 and 0. whe n the in tern al program or erase o peratio n is co mp leted , the dq 6 bit will stop to ggling. afte r the co mpletion o f a program ope ra tion, dq 6 will stop toggling for approximately 1 s. the device is the n read y for the n ext opera tion. the togg le bit (dq 6 ) is valid after the r ising edge of four th we# (or bef# ) pulse for program operation. for sector-, block- or chip-era se, th e to ggle bit (dq 6 ) is va lid a fte r the rising ed ge of sixth we# (or bef#) pulse. see figure 10 fo r toggle bit timin g dia- gram a nd figure 22 for a flowcha rt. data protection the SST34HF1621/1641 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protecti on noise/glitch protection: a we# or bef# pulse o f less tha n 5 ns will not initiate a write cycle. v dd power up/down detection: the write opera tion is inhibite d whe n v dd is less th an 1 .5v. write in hibit mo de: fo rcing oe# low, bef# hig h, or we# high will inhibit the write operation. this prevents i nadvert- ent write s during power-up or power-down. hardware bl ock pro tectio n the SST34HF1621 /164 1 provide a h ardware blo ck pro tec- tion wh ich prote cts the o uter most 4 kword in the larg er bank.the blo ck is pro tected wh en wp# is held low. se e fig ure 1 for block-protectio n locatio n. a user can disable block protection by drivin g wp# hig h thu s allowing e rase or program of data into th e pro tecte d se ctors. wp# must be held high prior to issuing th e write co mmand and rema in stable until after the e ntire write operation has completed. hardware reset (rst#) th e rst# pin provid es a h ardware metho d of resetting th e device to rea d array data . whe n th e rst# pin is h eld low for a t least t rp, any in-p rogress operation w ill terminate and retu rn to read mo de (see figure 1 8). wh en no in tern al program/erase operation is in progress, a minimum perio d of t rhr is req uired after rst# is drive n h igh before a valid read ca n take place (see figure 17). th e erase op eration th at has b een interru pte d ne eds to b e reinitiated after the d evice resumes n ormal o peratio n mod e to ensure data integrity. software data protection (sdp) th e SST34HF1621 /1641 provide the jedec stand ard software data protection sch eme for all data alteratio n operatio ns, i.e., program an d erase. any program operatio n requires the inclusion of the three-byte seq uence. th e three -byte load seque nce is u sed to in itiate the program operatio n, providing optimal pro tection fro m in adver tent write op erations, e.g., during the system p ower-up or power-down. any erase ope ra tion requ ires the inclusion of six-byte se quence. the sst34hf1 621/1641 are shippe d with the so ftware data protection per manently enabled. see ta ble 4 for the specific software comman d codes. dur- ing sdp command sequen ce, invalid comman ds w ill abort the device to rea d mode within t rc. the conten ts of dq 15 - dq 8 are ?do n?t care? during any sdp command se quence. common flash memory interface (cfi) th e sst3 4hf16 21/16 41 also contain the cfi informatio n to descr ib e the cha ra cteristics of the device. in orde r to ente r the cfi qu ery mo de, th e system must write th ree- byte se quence, same as software id entry command with 98h (cfi query co mma nd) to address 555h in the last byte seq uence. once the device enters the cfi query mode, th e system can rea d cfi data at the ad dresses given in tables 5 throug h 7. the system must write the cfi exit comman d to return to read mo de from th e cfi query mod e.
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 5 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 product identification the prod uct ide ntification mode ide ntifie s the devices as the sst34 hf16 21/1 641 a nd manu facturer as sst. this mode may be a ccesse d by software o peratio ns only. th e hardware device id re ad o peratio n, wh ich is typica lly u se d by programme rs ca nnot be used on this d evice b eca use of the shared lines betwee n flash a nd sram in the mu lti-ch ip packag e. therefore, ap plication of high voltag e to pin a 9 may d amage this device. users may use th e softwa re produ ct ide ntification op eration to ide ntify the pa rt (i.e., usin g th e device id) wh en using multip le manufa cturers in the same socket. for details, se e tables 3 and 4 fo r soft- wa re op eration , figure 14 for the software id entry an d read timing d ia gram a nd fig ure 23 for th e id e ntr y com- mand se quence flowchart. product identification mode exit/ cfi mode exit in order to return to the stan dard read mode, th e softwa re produ ct ide ntificatio n mode must b e exited. exit is accom- plished by issuing the software id exit command se quence, which re turn s th e device to the read mode. this co mmand may also b e used to reset the device to th e read mod e after any inadvertent transient co ndition that appa rently cau ses the device to behave abnor mally, e.g., not re ad co rrectly. please note th at th e software id exit/ cfi exit comma nd is igno red d uring a n internal program or erase o peratio n. see table 4 for software comman d co des, figure 16 for timing wave form and figu re 23 for a flowchart. sram operation with be s1# low, be s2 a nd be f# hig h, the sst34hf1 62x ope rates as 2 56k x8 o r 1 28k x1 6 cmos sram, an d the sst34 hf164 x o pera te s as 512 k x8 o r 256 k x1 6 cmos sram, with fully static op era tio n re quir - ing no e xter nal clo cks or timin g strobe s. the cios pin configu res the sram fo r x8 o r x16 sram op eration mod es. th e sst3 4hf16 2x sram is mapp ed into the first 25 6 kbyte /1 28 kword add ress space of th e device, and the sst3 4hf16 4x sram is m app ed into the first 512 kbyte/25 6 kword a dd ress sp ace. whe n bes1 #, bef# are hig h and bes2 is low, all memo ry ban ks are dese lecte d a nd the device enters stand by. re ad and write cycle times are equal. the control signals ubs# and l bs# provide a cce ss to the up per da ta byte and lower data byte. see ta ble 3 fo r sram read an d w rite data byte co ntrol mode s o f ope ration. sram read th e sram read operation o f the SST34HF1621 /16 41 is co ntrolled by oe# and bes1#, both h ave to be low with we# and bes2 high for the system to obtain d ata from th e outputs. bes1# and bes2 are used for sram b ank selec- tion. oe# is th e output contro l and is used to gate data from the ou tput pins. the da ta bus is in h ig h imp edance state when oe# is hig h. refer to the read cycle timing diagram, figure 3, for further details. sram write th e sram write op eration of the SST34HF1621 /164 1 is co ntrolled by we# and bes1# , both h ave to be low, bes2 have to be h ig h for the system to write to th e sram. durin g the word -write op eration , th e addresses a nd data are ref- erenced to the risin g e dge of e ither bes1#, we#, or th e falling edg e of bes2 whichever occurs first. the write time is measured fro m the la st fa lling ed ge of bes#1 or we# or the risin g edg e of bes2 to the first rising e dge of bes1 #, or we# o r the falling ed ge of bes2. refer to th e write cycle timing diagram, figures 4 and 5, for fur the r de tails. tab l e 1: p roduct i de n tific a tio n address data manufacturer?s id 0000h 00bfh devic e i d SST34HF1621 0001h 2761h sst34hf1641 0001h 2761h t 1. 2 523
6 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 523 ill b1.1 superflash memory (bank 1) i/o buffers superflash memory (bank 2) 2 mbit or 4 mbit sram a ms - a 0 dq 15 - dq 8 dq 7 - dq 0 a ms = most significant address bef# wp# sa lbs# ubs# we# oe# bes1# bes2 cios control logic rst# ry/by# address buffers address buffers f unctional b lock d iagram
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 7 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 1: SST34HF1621/1641, 1 m bit x 16 c oncurrent s uper f lash d ual -b ank m emory o rg a ni z at i on fffffh f8000h block 31 f7fffh f0000h block 30 effffh e8000h block 29 e7fffh e0000h block 28 dffffh d8000h block 27 d7fffh d0000h block 26 cffffh c8000h block 25 c7fffh c0000h block 24 bank 2 bffffh b8000h block 23 b7fffh b0000h block 22 affffh a8000h block 21 a7fffh a0000h block 20 9ffffh 98000h block 19 97fffh 90000h block 18 8ffffh 88000h block 17 87fffh 80000h block 16 7ffffh 78000h block 15 77fffh 70000h block 14 6ffffh 68000h block 13 67fffh 60000h block 12 5ffffh 58000h block 11 57fffh 50000h block 10 4ffffh 48000h block 9 47fffh 40000h block 8 3ffffh 38000h block 7 37fffh 30000h block 6 2ffffh 28000h block 5 27fffh 20000h block 4 1ffffh 18000h block 3 17fffh 10000h block 2 00ffffh 008000h block 1 007fffh 000fffh 000000h block 0 bank 1 bottom sector protection; 32 kword blocks; 1 kword sectors 4 kword sector protection (four 1 kword sectors) 523 ill f02.1 001000h
8 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 2: p in a ssignments for 56 - ball lfbga (8 mm x 10 mm ) c ombo m em o ry p in ou t tab l e 2: p in d escri ptio n symbo l pin n ame fu ncti on s a ms 1 to a 0 1. a ms = most sign if ica nt ad dress address inputs to provide flash address, a 19 -a 0 . to provide sram address, a 16 -a 0 for 2m and a 17 -a 0 for 4m sa address input (sram) to provide sram address input in byte mode (x8). when cios is v il , the sram is in byte mode and sa provides the most significant address input. when cios is v ih , the sram is in word mode and sa becomes a don?t care pin. dq 15 -dq 0 data inputs/outputs to output data during read cycles and receive input data during write cycles. data is internally latched during a flash erase/program cycle. the outputs are in tri-state when oe# is high or bes1# is high or bes2 is low and bef# is high. bef# flash memory bank enable to activate the flash memor y bank when bef# is low bes1# sram memory bank enable to activate the sram memor y bank when bes1# is low bes2 sram memory bank enable to activate the sram memor y bank when bes2 is high oe# output enable to gate the data output buffers we# write enable to control the write operations ubs# upper byte control (sram) to enable dq 15 -dq 8 lbs# lower byte control (sram) to enable dq 7 -dq 0 cios i/o configuration (sram) cios = v ih is word mode (x16), cios = v il is byte mode (x8) wp# write protect to protect and unprotect sectors from erase or program operation rst# reset to reset and return the device to read mode ry/by# ready/busy# to output the status of a program or erase operation ry/by# is a open drain output, so a 10k ? - 100k ? pull-up resistor is required to allow ry/by# to transition high indicating the device is ready to read. v ss ground v dd f power supply (flash) 2.7-3.3v power supply to flash only v dd s power supply (sram) 2.7-3.3v power supply to sram only nc no connection unconnected pins t2.5 523 523 56-lfbga ill p01.2 a11 a8 we# wp# lbs# a7 a15 a12 a19 bes2 rst# ubs# a6 a3 nc a13 a9 nc ry/by# a18 a5 a2 nc a14 a10 a17 a4 a1 a16 sa dq6 dq1 v ss a0 nc dq15 dq13 dq4 dq3 dq9 oe# bef# v ss dq7 dq12 v dds v ddf dq10 dq0 bes1# dq14 dq5 cios dq11 dq2 dq8 a b c d e f g h SST34HF1621/1641 8 7 6 5 4 3 2 1 top view (balls facing down)
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 9 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 tab l e 3: o perational m odes s election 1 mode bef# bes1# bes2 2 cios 3 oe# we# sa lbs# ubs# dq 0-7 dq 8-15 full standby v ih v ih x x x x x x x high -z hi gh-z xv il xxxxxx output disable v ih v il v ih xv ih v ih xxxhigh-z high-z v il v ih v ih xxxv ih v ih v il v ih xxv ih v ih xxxhigh-zhigh-z xv il flash read v il v ih xxv il v ih xxxd out d out xv il flash write v il v ih x x v ih v il xxx d in d in xv il flash erase v il v ih xx v ih v il xxx x x xv il sram read v ih v il v ih v ih v il v ih xv il v il d out d out v ih v il high -z d out v il v ih d out hi gh-z v ih v il v ih v il v il v ih sa x x d out hi gh-z sram write v ih v il v ih v ih xv il xv il v il d in d in v ih v il high -z d in v il v ih d in hi gh-z v ih v il v ih v il xv il sa x x d in hi gh-z product identification 4 v il v ih x x v il v ih x x x manufacturer?s id 5 device id 5 xv il t3.6 523 1. x can be v il or v ih , but no other value. 2. do not apply be f# = v il , bes 1# = v il and bes2 = v ih at the same time 3. sram i/o configuration input cios; v ih = x16 (word mo de ), v il = x8 (byte mode) 4 . so ftware mod e only 5. with a 19 -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst3 4hf16 21/ 16 41 de vice id = 2 76 1h, is rea d with a 0 = 1
10 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 tab l e 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle a ddr 1 data 2 ad dr 1 data 2 ad dr 1 data 2 addr 1 data 2 a ddr 1 data 2 ad dr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h soft ware id ent ry 5 5555h aah 2aaah 55h 5555h 90h cf i query entr y 5 5555h aah 2aaah 55h 5555h 98h soft ware id ex it/ cf i exit 6 5555h aah 2aaah 55h 5555h f0h t4.4 523 1. address format a 14 -a 0 (hex),a ddre ss a 15 - a 19 ca n be v il or v ih , but no other value, for the command sequence. 2. data format dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence. 3. wa = program word address 4. sa x for sector-erase; uses a 19 -a 11 ad dress lin es ba x for block-erase ; u ses a 19 -a 15 address lines 5. the device does not remain in software p roduct identification mode if powered down. 6. with a 20 -a 1 = 0; s st manu fact urer?s i d = 00b fh, is re ad with a 0 = 0 s st34 hf1 62 1/1 64 1 device id = 27 61 h, is read with a 0 = 1. tab l e 5: c f i q ue r y i dentification s tring 1 1. refer to cfi publicat ion 100 for more details. ad dr ess d ata data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primar y oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alter nate oem extended table (00h = none exits) 1ah 0000h t5.0 523
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 11 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 tab l e 6: s ystem i nterface i nformation ad dr ess d ata data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0004h typical time out for word-program 2 n s (24 = 16 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not suppor ted) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 0001h maximum time out for word-program 2 n tim es ty pical (2 1 x 2 4 = 32 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n tim es ty pical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n t im es ty pical (2 1 x 2 6 = 128 ms) t6.0 523 tab l e 7: d evi ce g eo me try i nformation ad dr ess d ata data 27h 0015h device size = 2 n byte (15h = 21; 2 21 = 2m bytes) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of byte in multi-byte wr ite = 2 n (00h = not suppor ted) 2bh 0000h 2ch 0002h number of erase sector/block sizes suppor ted by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 0003h y = 1023 + 1 = 1024 sectors (03ff = 1023) 2fh 0008h 30h 0000h z = 8 x 256 bytes = 2 kbyte/sector (0008h = 8) 31h 001fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 31 + 1 = 32 blocks (001f = 31) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.0 523
12 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 absolute maximum stress ratings (ap pli ed co nd itio ns gre ate r th an th ose li ste d u nd er ?abso lu te maxi mum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of th e de vice at the se con di ti on s o r co n ditio ns gr ea ter tha n tho se de fine d in th e op era tio na l se ction s o f th is d ata sheet is not implied. exposure to absolute maxi mum stress rati ng conditions may affect devi ce reliabi lity.) operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v dd 1 +0.3v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd 1 +1.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. v dd = v dd f an d v dds 2. outputs shorted for no more than one second. no more than one output shorted at a time. o pe rati ng r ange ran ge a mbi ent temp v dd commercial 0c to +70c 2.7-3.3v extended -20c to +85c 2.7-3.3v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 19 and 20
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 13 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 tab l e 8: d c o perating c haracteristics (v dd = v ddf and v dds = 2.7-3.3v) symbol parameter limits test conditions mi n max un its i dd active v dd current address input=v il /v ih , at f=1/ t rc min, v dd =v dd max, all dqs open read oe#=v il , we#=v ih flash 35 ma bef#=v il , bes1#=v ih , or bes2=v il sram 20 ma bef#=v ih , bes1#=v il , bes2=v ih concurrent operation 60 ma bef#=v ih , bes1#=v il , bes2=v ih writ e 1 flash 40 ma bef#=v il , bes1#=v ih , or bes2=v il , oe#=v ih sram 20 ma bef#=v ih , bes1#=v il , bes2=v ih i sb standby v dd current 3.0v 3.3v 40 75 a a v dd = v dd max, bef#=bes1#=v ih c , bes2=v il c i alp i rt auto low power mode 3.0v 3.3v res et v dd current 40 75 30 a a a v dd =v dd max, bef#=v ilc , we#=v ihc , all i/o=v ilc /v ihc reset=v ss 0.3v i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7 v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v olf flash output low voltage 0.2 v i ol =100 a, v dd =v dd min v ohf flash output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min v ols sram output low voltage 0.4 v iol =1 ma, v dd =v dd min v ohs sram output high voltage 2.2 v ioh =-500 a, v dd =v dd min t8 .6 523 1. i dd active while e ra se o r program is in prog re ss.
14 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 tab l e 9: r ecommended s ys tem p ow e r - up t im in g s symbo l parameter m in imu m un its t pu-read 1 power-up to read operation 100 s t pu-write 1 power-up to write operation 100 s t9 .1 523 1 . this pa ramete r is me asu re d o nly fo r in itial qu alificat io n a nd af ter a de sign or pro cess ch an ge tha t co uld affe ct th is pa ra me t er. tab l e 10 : c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1 . this pa ramete r is me asu re d o nly fo r in itial qu alificat io n a nd af ter a de sign or pro cess ch an ge tha t co uld affe ct th is pa ra me t er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t 10 .0 523 tab l e 11 : f lash r eliability c haracteristics symbol parameter minimum specification units test method n end 1 1 . this pa ramete r is me asu re d o nly fo r in itial qu alificat io n a nd af ter a de sign or pro cess ch an ge tha t co uld affe ct th is pa ra me t er. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t 11 .1 523
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 15 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 ac characteristics table 12: sram r ead c ycle t iming p arameters symbol parameter SST34HF1621/1641-70 SST34HF1621/1641-90 units min max min max t rcs read cycle time 70 90 ns t aas address access time 70 90 ns t bes bank enable access time 70 90 ns t oe s output enable access time 35 45 ns t byes ubs#, lbs# access time 70 90 ns t blzs 1 1 . this pa ramete r is me asu re d o nly fo r in itial qu alificat io n a nd af ter a de sign or pro cess ch an ge tha t co uld affe ct th is pa ra me t er. bes# to active output 0 0 ns t olzs 1 output enable to active output 0 0 ns t bylzs 1 ubs#, lbs# to active output 0 0 ns t bhzs 1 bes# to high-z output 25 35 ns t ohzs 1 output disable to high-z output 25 35 ns t byhzs 1 ubs#, lbs# to high-z output 35 45 ns t ohs output hold from address change 10 10 ns t 12 .3 523 table 13: sram w rite c ycle t im in g p arameters symbol parameter SST34HF1621/1641-70 SST34HF1621/1641-90 uni ts mi n max mi n max t wcs write cycle time 70 90 ns t bws bank enable to end-of-write 60 80 ns t aws address valid to end-of-write 60 80 ns t asts address set-up time 0 0 ns t wps write pulse width 60 80 ns t wrs writ e r ecovery t ime 0 0 ns t byws ubs#, lbs# to end-of-wr ite 60 80 ns t odws output disable from we# low 30 40 ns t oe ws output enable from we# high 0 0 ns t dss data set-up time 30 40 ns t dhs data hold from write time 0 0 ns t 13 .3 523
16 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 tab l e 14 : f lash r ead c ycle t im in g p arameters v dd = 2.7-3.3v symbol parameter SST34HF1621/1641-70 SST34HF1621/1641-90 un its minmaxminmax t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t clz 1 bef# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 bef# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t rp 1 rst# pulse width 500 500 ns t rhr 1 rst# high before read 50 50 ns t ry 1, 2 rst# pin low to read 150 150 s t1 4. 4 523 1 . this pa ramete r is me asu re d o nly fo r in itial qu alificat io n a nd af ter th e desig n o r proce ss cha ng e t hat cou ld a ffect this p aram et er. 2 . this pa ramete r ap plies to se cto r-erase an d b lock-e ra se ope ra tion s. this p aramet er do es not ap ply to chip -e ra se o pe ra tions. tab l e 15 : f lash p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 40 ns t cs we# and bef# setup time 0 ns t ch we# and bef# hold time 0 ns t oe s oe# high setup time 0 ns t oe h oe# high hold time 10 ns t cp bef# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this p arame ter is mea sured on ly for initial q ua lif ica tion an d a fte r a d esign o r p rocess cha nge th at cou ld af fect this p aramet er. we# pulse width high 30 ns t cph 1 bef# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t by 1 ry/by# delay time 90 ns t br bus recover y time 1 s t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t1 5. 3 523
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 17 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 3: sram r ead c ycle t iming d iagram figure 4: sram w rite c ycle t im in g d iagram (we# c ontrolle d ) 1 addressesa mss-0 dq 15-0 ubs#, lbs# a mss = most significant sram address oe# bes1# bes2 t rcs t aas t bes t oes t blzs t olzs t byes t bylzs t byhzs data valid t ohzs t bhzs t ohs 523 ill f15.0 t bes t aws addresses a mss-0 bes1# bes2 we# ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. if bes1# goes low or bes2 goes high coincident with or after we# goes low, the output will remain at high impedance. if bes1# goes high or bes2 goes low coincident with or before we# goes high, the output will remain at high impedance. because din signals may be in the output state at this time, input signals of reverse polarity must not be applied. t wcs t wps t wrs t asts t bws t bws t byws t odws t oews t dss t dhs 523 ill f16.2 note 2 dq 15-8, dq 7-0 valid data in note 2
18 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 5: sram w rite c ycle t im in g d iagram (ubs#, l bs# c ontrolled ) 1 addresses a mss-0 we# bes1# bes2 t bws t bws t aws t wcs t wps t wrs t asts t byws dq 15-8, dq 7-0 valid data in note 2 note 2 t dss t dhs ubs#, lbs# notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance. 2. because din signals may be in the output state at this time, input signals of reverse polarity must not be applied. 523 ill f18.0
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 19 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 6: f lash r ead c ycle t im in g d iagram figure 7: f lash we# c ontro lled w ord -p rogram c ycle t im in g d iagram 523 ill f04.0 address a 19-0 dq 15-0 we# oe# bef# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 523 ill f05.3 address a 19-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs t by bef# ry/by# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# we# t br t bp note: x can be v il or v ih , but no other value. valid
20 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 8: f lash bef# c ontro lled w ord -p rogram c ycle t im in g d iagram figure 9: f lash d ata # p o lling t iming d ia gr a m valid 523 ill f06.3 address a 19-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data word (addr/data) oe# bef# t bp t by ry/by# t br note: x can be v il or v ih , but no other value. 523 ill f07.2 address a 19-0 dq 7 data# data# valid data we# oe# bef# t oeh t oe t ce t oes t br
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 21 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 10: f lash t ogg le b it t im in g d iagram figure 11: f lash we# c ontro lled c hip -e rase t im in g d iagram 523 ill f08.3 address a 19-0 dq 6 we# oe# bef# t oe t oeh t ce two read cycles with same outputs valid data t br valid t br 523 ill f09.6 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# bef# six-byte code for chip-erase t sce t wp note: this device also supports bef# controlled chip-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 15) x can be v il or v ih , but no other value. t by ry/by#
22 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 12: f lash we# c ontro lled b lo ck -e rase t im in g d iagram figure 13: f lash we# c ontro lled s ector -e rase t im in g d iagram 523 ill f10.5 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# bef# six-byte code for block-erase t wp note: this device also supports bef# controlled block-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 15) ba x = block address x can be v il or v ih , but no other value. t by ry/by# valid t br t be 523 ill f11.5 address a 19-0 dq 15-0 we# 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# bef# six-byte code for sector-erase t se t wp note: this device also supports bef# controlled sector-erase operation. the we# and bef# signals are interchageable as long as minimum timings are met. (see table 15) sa x = sector address x can be v il or v ih , but no other value. t by ry/by# valid t br
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 23 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 14: f lash s o ftware id e ntry and r ead figure 15: f lash cfi e ntry and r ead 523 ill f12.6 address a 14-0 t ida dq 15-0 we# device id = 2761h for SST34HF1621 and 2761h for sst34hf1641 note: x can be v il or v ih , but no other value 5555 2aaa 5555 0000 0001 oe# bef# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 523 ill f13.2 address a 14-0 t ida dq 15-0 we# 5555 2aaa 5555 oe# bef# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih, but no other value.
24 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 16: f lash s o ftware id e xi t /c fi e xit figure 17: rst# t iming ( when no internal op eratio n is in prog res s ) figure 18: rst# t iming ( during s ecto r - or b lock -e rase operation ) 523 ill f14.3 address a 14-0 dq 15-0 t ida t wp t whp we# 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# bef# xxaa xx55 xxf0 note: x can be v il or v ih, but no other value 523 ill f29.0 ry/by# 0v rst# ce#/oe# t rp t rhr 523 ill f30.0 ry/by# ce# oe# t rp t ry t br rst#
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 25 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 19: ac i nput /o utput r eference w av ef or m s figure 20: a t es t l oad e xam ple 523 ill f19.0 reference points output input v it v iht v ilt v ot ac test in puts are driven at v ih t (0 .9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a lo gic ?0?. measureme nt referen ce points for inputs and outputs a re v it (0.5 v dd ) a nd v ot (0.5 v dd ). input rise a nd fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input hi gh test v ilt - v in p ut low test 523 ill f20.0 to tester to dut c l
26 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 21: w ord -p rogram a lg orithm 523 ill f21.4 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih, but no other value.
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 27 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 22: w ait o ptions 523 ill f22.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
28 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 23: s oftware p roduct id/cfi c ommand f lowcharts 523 ill f23.3 load data: xxaah address: 5555h software product id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h wait t ida return to normal operation note: x can be v il or v ih, but no other value.
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 29 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 figure 24: e rase c ommand s equence 523 ill f24.2 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih, but no other value.
30 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 product ordering information valid combinations for SST34HF1621 sst3 4h f16 21 -7 0- 4c- lfp sst3 4hf1 6 21 -7 0-4 c-l 1 p sst3 4h f16 21 -9 0- 4c- lfp sst3 4hf1 6 21 -9 0-4 c-l 1 p SST34HF1621-70-4e-lfp SST34HF1621-70-4e-l1p SST34HF1621-90-4e-lfp SST34HF1621-90-4e-l1p valid combinations for sst34hf1641 sst3 4h f16 41 -7 0- 4c- lfp sst3 4hf1 6 41 -7 0-4 c-l 1 p sst3 4h f16 41 -9 0- 4c- lfp sst3 4hf1 6 41 -9 0-4 c-l 1 p sst34hf1641-70-4e-lfp sst34hf1641-70-4e-l1p sst34hf1641-90-4e-lfp sst34hf1641-90-4e-l1p note: valid combinations are those products in mass production or will be in mass production. consult your sst sales re prese nta tive to co nfirm availab ility o f va lid combin atio ns a nd to de termin e availab ility o f n ew comb in atio ns. device speed suffix1 suffix2 sst34 h f16 x x - xxx -x x -x x pac ka ge mo dif ier p = 56 balls pa ckage ty pe lf = lfbga (8mm x 10mm x 1.4mm, 0.4mm ball size) l1 = lfbga (8mm x 10mm x 1.4mm, 0.45mm ball size) tempe rat ure ra nge c = commercial = 0c to +70c e = extended = -20c to +85c minimum endurance 4 =10,000 cycles read access speed 70 = 70 ns 90 = 90 ns bank split 1 = 12m + 4m sram density 0 = no sram 2 = 2 mbit 4 = 4 mbit flash density 16 = 16 mbit volta ge h = 2.7-3.3v
data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 31 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 packaging diagrams 56 - ba l l l ow - profile , f in e - pi tch b all g rid a rray (lf bga) 8 mm x 10 mm ss t p ackage c ode : lfp note: this package w ill be repl aced by l1p whi ch increases the bal l size from 400-micron to 450-micron. check with factory for migration schedule. a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 8 7 6 5 4 3 2 1 seating plane 0.32 0.05 1.30 0.10 0.12 8.00 0.20 0.40 0.05 (56x) a1 corner 10.00 0.20 0.80 5.60 0.80 5.60 56-lfbga-lfp-8x10-400mic-8 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. the actual shape of the corners may be slightly different than as portrayed in the drawing. 8 7 6 5 4 3 2 1 1mm
32 data sheet 16 mbit concurrent superflash + 2 / 4 mbit sram combomemory SST34HF1621 / sst34hf1641 ? 200 2 sili con st orag e te chno log y, i nc. s71 172 -05-0 00 2 /0 2 523 56 - ba l l l ow - profile , f in e - pi tch b all g rid a rray (lf bga) 8 mm x 10 mm ss t p ackage c ode : l1p a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 8 7 6 5 4 3 2 1 seating plane 0.35 0.05 1.30 0.10 0.12 8.00 0.20 0.45 0.05 (56x) a1 corner 10.00 0.20 0.80 5.60 0.80 5.60 56-lfbga-l1p-8x10-450mic-3 note: 1. although many dimensions are similar to those of jedec publication 95, mo-210, this specific package is not registered. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. the actual sha p e of the corners ma y be sli g htl y different than as p ortra y ed in the drawin g . 8 7 6 5 4 3 2 1 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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